1. Field of the Invention
Exemplary embodiments of the present invention relate to a semiconductor device design, and more particularly, to a semiconductor memory device which drives negative word lines.
2. Description of the Related Art
A negative word line driving method is a method performed by a word line driving circuit that drives word lines by applying a high voltage VPP to a word line to enable the word line and applying a voltage VBBW lower than a ground voltage VSS to the word line to disable the word line. In general, the ground voltage VSS is applied to a word line to disable the word line, but according to the negative word line driving method, a voltage VBBW lower than a ground voltage VSS is applied to the word line to disable the word line.
When the negative word line driving method is used, refresh characteristics and other AC parameters may be improved. In particular, since the voltage VBBW, used as a voltage level for disabling the word line, is lower than the ground voltage VSS, the data retention time of a cell is extended so as to reduce the use of a refresh cycle.
Also, when a voltage VCC, lower than the high voltage VPP, is used to enable a word line, write recovery time TWR may be improved. For these reasons, the negative word line driving method is adopted.
FIG. 1 is a block view illustrating a known semiconductor memory device adopting a negative word line driving scheme.
Referring to FIG. 1, the known semiconductor memory device includes a block selection address generation unit 10, a row decoder control unit 20, a sub-word line selection unit 30, a main word line selection unit 40, and a sub-word line driving unit 50.
To briefly have a look at the operation of the known semiconductor memory device, the block selection address generation unit 10 generates a block selection address BAX having block information in response to an active signal. The main word line selection unit 40 selects and drives a corresponding main word line MWLB (the “B” indicates that an inverted signal is transferred through the main word line) from among a plurality of main word lines (not shown) based on a portion (e.g., BAX<3:8> of the block selection address BAX. Meanwhile, the sub-word line selection unit 30 generates an output FXB for selecting a sub-word line SWL based on another portion (e.g., BAX<0:2> of the block selection address BAX. Further, the sub-word line driving unit 50 selects and drives a sub-word line SWL from among a plurality of sub-word lines (not shown) corresponding to the main word line MWLB selected by the main word line selection unit 40 based on the output FX of the sub-word line selection unit 30.
The row decoder control unit 20 generates a word line pre-charge signal WLOFF for disabling a word line. The sub-word line selection unit 30 and the main word line selection unit 40 are controlled based on the word line pre-charge signal WLOFF. Accordingly, while word lines are enabled based on the block selection address BAX, they are disabled based on the word line pre-charge signal WLOFF.
The arrows directed toward the constituent units 20 to 50 in FIG. 1 signify that the negative word line driving method is used. In other words, in each of the constituent units 20 to 50 a voltage VBBW lower than a ground voltage VSS is used as a power source for supplying a logic low level. In short, when a word line is disabled, the voltage VBBW, which is lower than the ground voltage VSS, is applied to the word line.
FIG. 2 is a circuit diagram illustrating the known semiconductor memory device adopting the negative word line driving scheme of FIG. 1 in more detail.
Referring to FIG. 2, among the constituent elements of the known semiconductor memory device adopting the negative word line driving scheme, the main word line selection unit 40 includes a main word line decoder 42 and a main word line signal generator 44. The main word line decoder 42 selects a corresponding main word line MWL among a plurality of main word lines (not shown) by decoding a portion (e.g., BAX<3:8>) of the block selection address BAX. The main word line signal generator 44 generates a main word line signal OP_MWLB to select between an active driving and a pre-charge driving of the main word line MWLB in response to an output signal DBC_MWL of the main word line decoder 42.
Also, the sub-word line selection unit 30 includes a sub-word line decoder 32 and a sub-word line signal generator 34. The sub-word line decoder 32 selects a corresponding sub-word line SWL among a plurality of sub-word lines (not shown) by decoding a portion (e.g., BAX<0:2>) of the block selection address BAX. The sub-word line signal generator 34 generates a sub-word line signal FX, which is used to drive the selected sub-word line, in response to an output signal DEC_SWL of the sub-word line decoder 32.
The sub-word line driving unit 50 includes a first sub-word line driver 52 and a second sub-word line driver 54. The first sub-word line driver 52 drives the corresponding sub-word line SWL with a voltage based upon the sub-word line signal FX or a negative word line voltage VBBW in response to the main word line signal OP_MWLB. The second sub-word line driver 54 drives the corresponding sub-word line SWL with the negative word line voltage VBBW in response to a sub-word line bar signal FXB.
Referring to FIG. 2, the pre-charge operation of the known semiconductor memory device adopting the negative word line driving scheme is described hereafter.
First, before the pre-charge operation is performed, the semiconductor memory device may be in the state of an active operation, and therefore, the voltage level on both the main word line MWLB and the sub-word line SWL may be at a logic high level equal to the high voltage VPP.
When the pre-charge operation is performed on the semiconductor in the activation state, a main word line decoding signal DEC_MWL generated in the main word line decoder 42 and a sub-word line decoding signal DEC_SWL generated in the sub-word line decoder 32 transition to a logic low level equal to the negative word line voltage VBBW. Accordingly, the main word line signal OP_MWLB and the sub-word line bar signal FXB transition to a logic high level equal to the high voltage VPP, and a sub-word line driving selection signal FX transitions to a logic low level equal to the ground voltage VSS. As a result, the main word line MWLB selected by the main word line decoder 42 is driven with the high voltage VPP, and the sub-word line SWL selected by the sub-word line decoder 32 is driven with the negative word line voltage VBBW.
However, there are several concerns regarding the pre-charge operation of the known semiconductor memory device adopting the negative word line driving scheme.
First, in order to change the sub-word line SWL from the active state to the pre-charge state, the sub-word line SWL is disconnected from the high voltage VPP end and directly connected to a negative word line voltage VBBW end. Therefore, noise may be temporarily applied to the negative word line voltage VBBW end causing the level of the negative word line voltage VBBW to increase for a predetermined time. When this phenomenon occurs, off-leakage current is generated in many cell transistors which sustain a voltage level by receiving the negative word line voltage VBBW. Thus, the voltage level may not be sustained for a sufficient time.
Second, the sub-word line bar signal FXB swings between the high voltage VPP and the negative word line voltage VBBW and the negative word line voltage VBBW and the high voltage VPP have a great voltage difference. Moreover, the negative word line voltage VBBW and the high voltage VPP, having this great voltage difference, are applied to the source and drain ends of an NMOS transistor EN5 in a sub-hole region at a moment when the sub-word line SWL is pre-charged and driven. For this reason, the NMOS transistor EN5 of a sub-hole region is deteriorated, and thus, the size of current leaking from the high voltage VPP end toward the negative word line voltage VBBW end is increased. As a result, stand-by current of the semiconductor memory device may be increased.
Third, since a pre-charge operation is performed when the a logic high level voltage equal to the high voltage VPP is applied to a gate end of the NMOS transistor EN5 of the sub-hole region, much current flows through the NMOS transistor EN5 temporarily, causing a short phenomenon between a bit line contact of a gate end and a bit line contact of a source end in the NMOS transistor EN5. Therefore, the semiconductor memory device may fail.